Vacuum sputter cleaning techniques and vacuum plating cleaning techniques have been widely employed in the prior art to fabricate semiconductor devices. For example, U.S. Pat. No. 3,410,774 to Barson, et al, assigned to the instant assignee, describes a method and apparatus for reverse sputtering selected electrically exposed areas of a cathodically biased work piece in order to clean the exposed areas. U.S. Pat. No. 3,401,055 to Langdon, et al, assigned to the instant assignee, discloses a method of vacuum vapor depositing a metal layer through a mask located between the substrate to be plated and the evaporation source. In such prior art vacuum technology applications to semiconductor device fabrication, a semiconductor substrate 12, composed of a material such as silicon, is covered by an insulating layer 7 having a window 11 therethrough exposing a preformed electrode 9, as shown in FIG. 1. In this example, a first step of the operation is to deposit a layer of metal alloy 13 onto the electrode 9 to serve as the base for a solder contact 14 for subsequent joining to a semiconductor module, as is shown in FIG. 2. The prior art process and apparatus for carrying out this deposition is illustrated in FIG. 3, wherein a vacuum chamber 1 capable of sustaining a vacuum within its confines 2, by means of a vacuum pump 3, supports an anode 4, the mask 8, and the substrate 12, as shown. In order to clean the electrode layer 9 prior to the deposition of the metal alloy layer 13, an inert gas is introduced into the chamber 2 from the reservoir 7 and is ionized at the anode 4, producing the ions 6. The power supply 5 has its positive pole connected to the anode 4 and its negative pole connected to the mask 8 and the semiconductor wafer 12 so that the ions 6, which are charged, will be accelerated toward the mask 8. Those ions which are aligned with the windows 10 in the mask 8 will be propelled through the windows 10 toward the semiconductor substrate 12 and will collide with the surface of the metal electrode layer 9, thereby removing any unwanted oxide coating so as to perform the desired cleaning operation. The process of carrying out this reverse sputtering cleaning operation raises the temperature of the mask 8 and of the substrate 12. Since the mask 8 must undergo repeated exposures to the corrosive field of accelerated ions 6 during repeated usages of the sputtering apparatus, the mask 8 must be composed of a material which is highly resistant to sputtering, for example molybdenum. Although the coefficient of thermal expansion for molybdenum, which is .alpha..sub.Mo =5.5.times.10.sup.-6 /.degree. C., is greater than the coefficient of thermal expansion for silicon, which is .alpha..sub.Si =3.0.times.10.sup.-6 /.degree. C., since prior art applications of the sputtering process were directed to relatively small overall dimensions for the workpiece 12 and permitted relatively large tolerances for the resulting image position, the difference in the coefficient of thermal expansion for the mask 8 and the silicon substrate 12 was not considered to be significant. This is born out by the comment by Barson, et al, at column five, lines 51 through 55.
However, when the prior art reverse sputtering cleaning operation is applied to a relatively large semiconductor wafer having refined manufacturing tolerances, the differential expansion between the molybdenum mask and the semiconductor substrate 12 over the resultant temperature excursion of between room temperature and approximately 300.degree. centrigrade, causes a substantial yield loss due to the resultant inaccuracy in the image positioning. This problem is compounded when vacuum metal evaporation of the layers 13 and 14 is desired to immediately follow the reverse sputter cleaning operation, since the resultant location of the deposited layers 13 and 14 will not coincide with the location of the window 11 exposing the electrode 9 on the semiconductor substrate 12.
One technique for reducing the effects of this problem is disclosed in the publication by C. E. Benjamin, "FIXTURE DESIGN TO REDUCE METAL MASK/SILICON WAFER THERMAL MISMATCH EFFECTS," IBM Technical Disclosure Bulletin, Vol. 19, No. 7, December 1976. In this publication, tooling reduces the misalignment problems inherent in heated-substrate metal-masked evaporation of semiconductor device wafer thin-film patterns by up to a factor of 2 over previous designs. It employs a technique for constraining a spring-bias clamped silicon wafer 12 and metal evaporation mask 8 to expand thermally only in a radial direction, without obscuring any mask or wafer active areas. This technique forces the mask 8 and spring to expand only radially. Three pins and oblong slots in both the mask and spring are used. They are roughly equally spaced (about 120.degree. apart) around a circle. The long axes of the slots are radial, so that expansion of the mask and spring exert forces against the sides of the slots, making any movement only radial, with the centers effectively fixed with respect to the tooling. The peripheries of both the mask and spring " float" vertically and are horizontally constrained only by the pins in the radial slots, effectively tying the center of the wafer 12 to the center of the mask 8 and permitting unconstrained radial expansion (at different rates) of all parts. The base makes contact with the top ring outside the peripheries of the mask 8, wafer 12 and spring so that the mask is only pressed against the bottom surface of the top ring by pressure (through the wafer) from the leaf spring. The net result of constraining the centers of the mask 8 and wafer 12 together is that the maximum thermal mismatch during a hot-substrate evaporation will be only half that which exists when the mask 8 and wafer 12 are constrained at a point on (or near) the periphery. This is important from a device reliability point of view, since such misalignment while hot during evaporation can cause the metal alloy layer 13 to incompletely cover via hole 11, resulting in gross intermetallic formation and subsequent contact failure.
Although this technique can reduce by a factor of two, the effects of thermal coefficient of expansion mismatch, the resultant misalignments for the new larger semiconductor wafers and smaller semiconductor chip structures still produce significant production yield losses. Furthermore, if there is a non-uniform spring pressure around the periphery of the wafer due to the presence of foreign matter, then the point where the mask and wafer are relatively stationary is no longer the centroid of the mask but, instead, the point will be along its edge. This negates any improvement which the fixture might otherwise provide to the misalignment problem.